1. Field of the Invention
The invention relates to a pattern of a dielectric layer, and more particularly to a method of patterning a dielectric layer with a low dielectric constatnt k.
2. Description of the Related Art
In the semiconductor fabrication process, as the dimension of devices on a chip becomes smaller and smaller, the density of interconnect pitch is higher and higher. For a common dielectric layer, for example, a silicon oxide layer, due to the high dielectric constant, a higher RC delay is easily caused. Therefore, this kind of dielectric layer is not used as an inter-metal dielectric (IMD) in a high speed IC any longer. To apply a low k dielectric layer has the advantage such as reducing the interconnection parasitic capacitance, consequently reducing the RC delay, or mitigating the cross talk between metal lines, hence, the operation speed is improved. Hence, the low k dielectric layer is a very popular IMD material used in a high speed IC.
A common low k dielectric layer comprises organic polymers, for example, flare and parylene which are very suitable for used as an IMD.
FIG. 1A to FIG. 1D show the process of fabricating metal interconnects. Over a substrate 10 having a metal wiring layer 11 formed thereon, a dielectric layer 12 is formed, for example, using chemical vapour deposition (CVD) or spin-on-glass (SOG) to deposit organic polymer with a thickness of about 3000 .ANG. to 10000 .ANG.. An insulation masking layer 13 such as a silicon oxide layer is formed on the dielectric layer 12 as a hard mask for the subsequent etching process. The insulation masking layer 13 is formed, for example, by CVD with silane (SiH.sub.4) and oxygen, and tetra-ethyl-oxy-silicate (TEOS) as reacting gas. Using photolithography, a photo-resist layer 14 is formed and patterned on the insulation masking layer 13.
Referring to FIG. 1B, using the photo-resist layer 14 as a mask, the insulation 1 0 masking layer 13 and the dielectric layer 12 are etched to form an opening 12 and to expose the metal wiring layer 11.
Referring to FIG. 1C, using a plasma containing oxygen as a cleaning agent, the photo-resist layer 14 is removed. Similar to the material contained in the photo-resist layer 14, the material contained in the dielectric layer 12 has a large proportion of carbon. Thus, part of the dielectric layer 12 is removed while removing the photo-resist layer 14.
Referring to FIG. 1D, after removing the photo-resist layer, a bowing side wall 16 is formed within the opening 15. In the subsequent process for forming conductive material, the step coverage is affected by the formation of the bowing side wall. Therefore, the stability and reliability of the devices are degraded.
In the he above method, the formation of a low k dielectric layer 12 in the process of interconnection has quite a few disadvantages. While removing the photo-resist layer 14, since the dielectric material is very similar to the photo-resist material, for example, both containing a large proportion of carbon, part of the low k dielectric layer 12 within the opening 15 is removed too. A bowing side wall 16 is thus formed within the opening 15. The bowing side wall 16 causes difficulty during the subsequent deposition process, and therefore, a poor step coverage is resulted. The conductivity for interconnects and the stability for devices are degraded. The degradation is more obvious as the dimension of and distances between devices becomes smaller and smaller.